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Wednesday, August 14 • 1:00pm - 2:15pm
Exploring Emerging Technologies in the HPC Co-Design Space

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Recent trends in HPC have forced our community to reexamine the full spectrum of architectures, software, and applications that constitute our HPC ecosystem. Architectural trends, such as heterogeneous processing and nonvolatile memory, are emerging in response to concerns about energy-efficiency and reliability. Meanwhile, applications are being redesigned so that they achieve new scientific objectives, expose prodigious amounts of hierarchical parallelism, and carefully orchestrate data movement. In what we have termed 'co-design,' teams of architects, software designers, and applications scientists, are working collectively to realize an integrated solution. Not surprisingly, this design space can be massive, uncertain, and discontinuous. To assist in this design space exploration, our team has recently developed a number of techniques for modeling, simulating, and measuring these future systems in order to predict performance, power, and reliability. For example, our Aspen (Abstract Scalable Performance Engineering Notation) performance modeling language allows users to compose and solve arbitrary performance modeling questions quickly and rigorously when compared to the traditional manual approach.


Speakers
JV

Jeffrey Vetter

Jeffrey Vetter, Ph.D., holds a joint appointment between Oak Ridge National Laboratory (ORNL) and the Georgia Institute of Technology (GT). At ORNL, Vetter is a Distinguished R&D Staff Member, and the founding group leader of the Future Technologies Group in the Computer Science and Mathematics Division. At GT, Vetter is a Joint Professor in the Computational Science and Engineering School of the College of Computing, the Principal... Read More →


Wednesday August 14, 2013 1:00pm - 2:15pm
College of Business Auditorium

Attendees (5)